Modeling and Estimating Leakage Current in Pass Transistor Logic Networks
نویسندگان
چکیده
This paper reviews the modeling of subthreshold leakage current and proposes an estimation method for passtransistor logic circuit. The estimation method takes into account the subthreshold current at the output buffer as well as in the logic network, where only single offtransistors are responsible for the standby current during the steady state analysis. The proposed leakage model has been validated through spice simulation, considering an 130nm CMOS technology, with good correlation of the results.
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